Semiconductor memories, such as dynamic random access memories (DRAMs), are widely used in computer systems for storing data. A DRAM memory cell typically includes an access field-effect transistor (FET) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations. The data charges on the storage capacitor are periodically refreshed during a refresh operation.
Memory density is typically limited by a minimum lithographic feature size (F) that is imposed by lithographic processes used during fabrication. For example, the present generation of high density dynamic random access memories (DRAMs), which are capable of storing 256 Megabits of data, require an area of 8F2 per bit of data. There is a need in the art to provide even higher density memories in order to further increase data storage capacity and reduce manufacturing costs. Increasing the data storage capacity of semiconductor memories requires a reduction in the size of the access FET and storage capacitor of each memory cell. However, other factors, such as subthreshold leakage currents and alpha-particle induced soft errors, require that larger storage capacitors be used. Thus, there is a need in the art to increase memory density while allowing the use of storage capacitors that provide sufficient immunity to leakage currents and soft errors. There is also a need in the broader integrated circuit art for dense structures and fabrication techniques.
Flash memory cells are one possible solution for high density memory requirements. Flash memories include a single transistor, and with high densities would have the capability of replacing hard disk drive data storage in computer systems. This would result in delicate mechanical systems being replaced by rugged, small and durable solid-state memory packages, and constitute a significant advantage in computer systems. What is required then is a flash memory with the highest possible density or smallest possible cell area.
The continuous scaling, however, poses problems even for flash memories since the single transistor in the flash memory has the same design rule limitations of conventional MOSFET technology. That is, the continuous scaling to the deep sub-micron region where channel lengths are less than 0.1 micron, 100 nm, or 1000 Å causes significant problems in the conventional transistor structures. As shown in FIG. 1, junction depths should be much less than the channel length of 1000 Å, or this implies junction depths of a few hundred Angstroms. Such shallow junctions are difficult to form by conventional implantation and diffusion techniques. Extremely high levels of channel doping are required to suppress short-channel effects such as drain-induced barrier lowering; threshold voltage roll off, and sub-threshold conduction. Sub-threshold conduction is particularly problematic in MOSFET technology as it reduces the charge storage retention time on the capacitor cells. These extremely high doping levels result in increased leakage and reduced carrier mobility. Thus making the channel shorter to improve performance is negated by lower carrier mobility.
Therefore, there is a need in the art to provide improved flash memory densities while avoiding the deleterious effects of short-channel effects such as drain-induced barrier lowering; threshold voltage roll off, and sub-threshold conduction, increased leakage and reduced carrier mobility. At the same time charge storage retention time must be maintained.